1. Field of the Invention
This invention relates to logic circuits for the transmission of data signals between components in a computer system, and more particularly to circuits for accessing a variable width data bus with a variable width data field and aligning the field on the bus.
2. Description of the Prior Art
There is a large segment of the data processing prior art directed to the transmission of data in fields or blocks, via parallel channels and busses, between processors, storage units, buffers, display terminals, input/output devices and the like. Problems occur in the prior art structures in techniques involving in bus steering and, different data formats (i.e , data widths and parallel interfacing.)
Some examples of typical prior art references in this environment include U.S. Pat. No. 4,126,897 entitled "Request Forwarding System," issued Nov. 21, 1978 to Capowski et al which describes a system wherein requests are forwarded from plural input/output channels to shared main storage. Variation in word widths are identified by tags such that "EOT" represents a "1-wide" request and a "QW" tag represents a "4-wide" request.
In U.S. Pat. No. 4,057,846 entitled "Bus Steering Structure For Low Cost Pipelined Processor Systems," issued Nov. 8, 1977 to Cockerill et al, a system is described including logic circuitry which provides a control function to steer data over the proper bus structures for interconnecting the processor, the memory and the input/output devices. No variable word problems are involved.
Likewise, Misunas et al (U.S. Pat. No. 4,174,536) discloses a system with a message routing switch wherein serial and parallel interfaces are associated with input/output ports. Davis et al (U.S. Pat. No. 4,075,691) and Larson et al (U.S. Pat. No. 4,079,452) show control systems using serial interface adapters and parallel interface adapters. Labeye-Voisin et al (U.S. Pat. No. 4,115,856) and Hostein (U.S. Pat. No. 4,034,346) show interfaces using parallel to serial conversion.
U.S. Pat. No. 4,159,534 (Gelson, Jr. et al), U.S. Pat. No. 4,070,710 (Sukonich et al), U.S. Pat. No. 4,004,283 (Bennett et al), U.S. Pat. No. 4,133,030 (Huettner et al), U.S. Pat. No. 4,205,373 (Shah et al) and U.S. Pat. No. 4,128,883 (Duke et al) show systems using device, channel and interface adapters for coupling to a bus.
In U.S. Pat. No. 3,949,375 (Ciarlo) a pair of 16-bit registers couple on a I/O bus to various display devices. In U.S. Pat. No. 3,500,466 (Carleton), a multiplexor is shown which couples different data sets through bit buffers to a common multi-line bus, and in U.S. Pat. No. 3,665,409 (Miller et al) a signal translator is shown for "skewing" or shifting data.
None of the prior art references provides a system for interfacing between a variable width data bus and a variable width data field by the "wrapping around" of "overflow" bits as is provided in the present invention.